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You can reach me at mohan@cs.virginia.edu

About Me

I currently work for SanDisk in Milpitas, CA. I graduated with a Ph.D in Computer Science from University of Virginia in December 2015.

Advisors

Professor Mircea Stan and Professor Kevin Skadron

Research

My dissertation addresses the power, reliability and scalability challenges of NAND flash based storage systems by modeling the metrics, evaluating the tradeoff between the metrics and exploring the design space to build application optimal storage systems. I also worked on redesigning the memory hierarchy with Storage Class Memory (SCM) technologies like Spin Torque Transfer RAM (STT-RAM). I have been part of the following projects:
*) NAND Power Modeling : Developed FlashPower, a detailed analytical model for flash memory chip energy dissipation. Validated the model with data from real chip measurements and used the model to optimize memory architecture for power consumption.
*) NAND Reliability Modeling : Developed FENCE, an analytical model to understand the factors affecting NAND reliability. Used the model to quantify the impact of system operating conditions like write frequency and temperature on flash failure mechanisms like endurance and data retention.
*) Improving Endurance of Data center SSDs : Proposed and evaluated novel SSD firmware algorithms that exploit trade-offs between endurance and data retention to increase endurance of data center SSDs.
*) Cache design using STT-RAM : Explored architecture and circuit level techniques that reduce the write energy and latency of STT-RAM and use them to design caches.

Publications (Google Scholar)

Copyright: Institutions like IEEE, ACM hold the copyrights on the papers listed below. Please respect the copyright claims of these organizations before accessing and distributing these papers. These papers are distributed for academic/educational purposes only.

7. Vidyabhushan Mohan, Trevor Bunker, Laura Grupp, Sudhanva Gurumurthi, Mircea R. Stan and Steven Swanson. Modeling Power Consumption of NAND Flash Memories Using FlashPower. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Issue 7, July 2013.
6. Vidyabhushan Mohan, Sriram Sankar and Sudhanva Gurumurthi. reFresh SSDs: Enabling High Endurance, Low Cost Flash in Datacenters. University of Virginia, Technical Report, CS-2012-05. May 2012. Presented at Flash Memory Summit, August 2012. [ppt]
5. Anurag Nigam, Clint Smullen, Vidyabhushan Mohan, Eugene Chen, Sudhanva Gurumurthi and Mircea R. Stan. Delivering on the Promise of Universal Memory for Spin-Transfer Torque RAM (STT-RAM). International Symposium on Low Power Electronics and Design (ISLPED). Fukuoka, Japan. August 2011.
4. Clint Smullen, Vidyabhushan Mohan, Anurag Nigam, Sudhanva Gurumurthi and Mircea R. Stan. Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches. The 17th IEEE Symposium on High Performance Computer Architecture (HPCA-17), February 2011.
3. Vidyabhushan Mohan, Taniya Siddiqua, Sudhanva Gurumurthi and Mircea R. Stan. How I Learned to Stop Worrying and Love Flash Endurance. 2nd Workshop on Hot Topics in Storage and File Systems (HotStorage), Co-located with USENIX Annual Technical Conference, Boston, MA. June 2010.
2. Vidyabhushan Mohan, Sudhanva Gurumurthi and Mircea R. Stan. FlashPower: A Detailed Power Model for NAND Flash Memory. Design, Automation and Test in Europe (DATE), Dresden, Germany. March 2010.
1. Srinath Sridharan, Srinivasan Thirunarayanan, Vidyabhushan Mohan. Implementation of .NET CLR on FPGAs. In the poster session of the 12th International Conference on High Performance Computing (HiPC), December 2005.

Thesis/Dissertation

Vidyabhushan Mohan. Towards Building Energy Efficient, Reliable and Scalable NAND Flash Based Storage Systems.. Ph.D. Dissertation. University of Virginia, Charlottesville. December 2015. [presentation]

Vidyabhushan Mohan. Modeling the Physical Characteristics of NAND Flash Memory. Master's Thesis. University of Virginia, Charlottesville. May 2010. [presentation]

Vidyabhushan Mohan. Implementation of .NET CLR on FPGAs. Bachelor's Thesis. College of Engineering, Guindy, Anna University. April 2006.

Undergraduate Education

I received my Bachelor's degree in Computer Science and Engineering from College of Engineering, Guindy, Chennai, India in 2006. I was advised by Professor Ranjani Parthasarathi.

News

July 2016: Finished San Francisco Full Marathon. Time: 4hrs 55 mins.
October 2015: Successfully defended my dissertation.
September 2014: Passed Ph.D. dissertation proposal.
July 2014: Finished San Francisco Full Marathon. Time: 5hrs and 7 mins.
March 2013: Joined the ESS division in SanDisk as a Senior Research Engineer.
March 2013: Rambus internship completed.
January 2013: Journal paper in Transactions on Computer Aided Design accepted.
August 2012: Presented my work on refresh SSDs at Flash Memory Summit, held in Santa Clara.
May 2012: Internship in Rambus.
August 2011: Google internship completed.
July 2011: Finished San Francisco Full Marathon. Time: 5hrs and 3 mins.
Jun 2011: Received L. William Ballard Jr. Fellowship from School of Engineering and Applied Sciences, UVa.
May 2011: Drove cross country from Charlottesville, VA to San Francisco, CA. Our route.
Apr 2011: Completed Ph.D Qualifying Examination. Details here.
Apr 2011: Internship offer from Seagate.
Mar 2011: Internship offer from Google.
Mar 2011: Presented a poster at NVMW'2011.
Feb 2011: Attended HPCA 2011.
Nov 2010: HPCA paper accepted.
Nov 2010: Finished Suntrust Richmond Full marathon. Time: 5hrs and 20 mins.
Sep 2010: Invited talk in IBM TJ Watson Research Center, Hawthorne, NY.
Jun 2010: Presented a paper in HotStorage, in Boston, MA
May 2010: Received my Master's degree.
Mar 2010: Presented a paper in DATE, in Dresden, Germany.